In modern electronics we observe a trend towards ever higher levels of integration. More functionality has to fit in ever smaller spaces. This trend extends over all industry sectors such as the consumer, automotive and industrial markets. While this has been driving the chip industry for several decades, we now observe that the interconnects are increasingly preventing smaller form factors.
The answer to this has been to make the PCBs flexible to fit into given spaces. However, the design tools used for PCBs are still largely planar and have to be adapted to this ‘3D aspect’ of PCB design. Also the effect of the bending on the PCB performance, such as signal integrity and emission has to be studied. This is becoming an increasing concern as the data rates go up.
In this webinar we demonstrate a workflow that can generate 3-dimensional PCB models from planar layouts that can be used in simulations to study the effect of the bending on the PCB performance. We will give design guidelines that can be used to avoid common problems in flexible printed circuits.
Dr. Klaus Krohne – Market Development Manager, CST
Dr. Klaus Krohne received his electrical engineering degree (Dipl.-Ing.) from the Darmstadt University of Technology in Germany in 2001 and a PhD Degree (Dr. sc.) from the Swiss Federal Institute of Technology in Zurich in 2007. From 2007 to 2009, he worked as a research fellow at the A*STAR Institute of High Performance Computing in Singapore. He is now CST’s* Market Development Manager for EDA.